Western Digital has officially announced today that they have successfully developed the next generation 3D NAND technology, BiCS3 with 64 layers of vertical storage capability. The pilot production was commenced in Yokkaichi Japan joint venture facilities and the expected initial output will be late this year.
The BiCS3 will be initially deployed in 256 gigabit capacity and it will be available in a range of capacities up to half a terabit on single piece of chip. The said chip was developed by Western Digital and its manufacturing partner Toshiba. The company is expecting a volume of shipments in the BiCS3 for the retail market in the fourth quarter of 2016 and they'll begin the OEM sampling this quarter.
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| BiCS3 chips |
“The launch of the next generation 3D NAND technology based on our industry-leading 64 layer architecture reinforces our leadership in NAND flash technology,” said Dr. Siva Sivaram, executive vice president, memory technology, Western Digital.
“BiCS3 will feature the use of 3-bits-per-cell technology along with advances in high aspect ratio semiconductor processing to deliver higher capacity, superior performance and reliability at an attractive cost. Together with BiCS2, our 3D NAND portfolio has broadened significantly, enhancing our ability to address a full spectrum of customer applications in retail, mobile and data center.”
The BiCS3 will be initially deployed in 256 gigabit capacity and it will be available in a range of capacities up to half a terabit on single piece of chip. The said chip was developed by Western Digital and its manufacturing partner Toshiba. The company is expecting a volume of shipments in the BiCS3 for the retail market in the fourth quarter of 2016 and they'll begin the OEM sampling this quarter.
